1) Field of the Invention
This invention relates generally the fabrication of doped regions in a semiconductor device and more particularly to a method of forming a lightly doped drain (LDD) structure for a semiconductor device.
2) Description of the Prior Art
Extensive research and development is being conducted to micronization semiconductor elements. In particular, the micro-miniaturization of an insulated gate effect transistor called a metal oxide semiconductor FET (MOSFET) is remarkable. The miniaturization of a MOSFET is achieved by shortening a width of a gate electrode in channel length direction. The shorter gate electrode naturally shortens the length of a channel region thereunder. The short channel improves transistor performance. The length of time required for carriers to pass through the channel portion is reduced, thus resulting in a higher speed along with greater integration. When the gate electrode is shortened, however, hot electrons are produced by a short channel effect, thus bringing about threshold voltage variation or lowering of channel conductance. Namely, in a conventional structure a channel region composed of a first conductive type impurity diffused layer of low concentration is put between a source region and a drain region composed of a second conductive type impurity diffused layer of high concentration, an electric field applied to the vicinity of a boundary among a source region, a drain region and a channel region is increased in a state that voltage is applied between the source region and the drain region as the channel region is narrowed. As a result, the operation of the MOSFET becomes very unstable.
A new structure of a MOSFET has been developed for the purpose of controlling such a short channel effect. The LDD has a layer structure of a high impurity concentration and a shallow low impurity concentration region formed in a source region and a drain region, and the low concentration region of these regions stretches out a little towards the gate electrode. It has become possible to reduce the electric field produced in the vicinity of the boundary among the source region, the drain region, and the channel region, thereby to stabilize the operation of the element by the LDD.
An example of a method of manufacturing a conventional LDD insulated gate field effect transistor will be shown in FIGS. 6A to 6C. First, as shown in FIG. 6A, a gate electrode 104 is formed over a gate oxide film 103 on a surface of a p-type semiconductor substrate 101 surrounded by a field insulating film 102. The gate oxide film 103 and the gate electrode 104 are formed through a film forming process and a photolithography process.
Then, n-type impurity diffused regions 105 and 106 having comparatively low impurity concentration are formed in a self-aligned matter by ion implantation using the gate electrode 104 and the field insulating film 102 as a mask.
Then, after an insulating film such as PSG and silicon oxide are formed by chemical vapor deposition (CVD) on the whole body so as to cover the gate electrode 104 and the n-type impurity diffused regions 105 and 106, the insulating film is etched anisotropically in a perpendicular direction and made to remain locally on the side of the gate electrode 104 as shown in FIG. 6B.
The remaining insulating film is called a spacer or a sidewall in general. N+ type impurity diffused regions 108 and 109 having high impurity concentration such as those shown in FIG. 6C are formed in a self-aligning manner by ion implantation for a second time using the gate electrode 104 and a side wall 107 as the mask.
Then an interlayer insulating film 110 is formed on the whole body, and contact holes are formed therethrough, thereby to connect a source electrode 111 and a drain electrode 112 to the N+ type impurity diffused regions 108 and 109. With this, an insulated gate fields effect transistor having a LDD structure is formed in an element forming region. A process of manufacturing an n-type MOS has been described above but a p-type MOS is also formed through an almost similar process.
According to the process described above, however, the side wall 107 on the side of the gate electrode 104 vary in width. This varying width is caused by the anisotropic etching. The irradiation angle of ions used for etching becomes uneven and the width of the sidewall 107 varies when the substrate becomes large in size.
In a conventional LDD, it has been impossible to increase the aspect ratio without restriction because of the inherit limitation in the sidewall spacer process. The width of the sidewall 107 formed by the anisotropic etching depends on the height of the gate electrode 104. Normally, the width of the sidewall (e.g., spacers) 107 reaches 20% or more of the height of the gate electrode 104. When the width of the sidewall 107 becomes wider, the n-type impurity diffuse (low concentration) regions (redefined smaller regions -see FIG. 6c) 105 and 106 become wider and the resistance between a source and a drain is increased, thus deteriorating transistor characteristics.
Practitioners in the art have attempted to improve the LDD structure. For example, U.S. Pat. No. 5,518,940 (Hodate et al.) teaches a method of forming LDD regions adjacent to a gate using a photoresist layer as a spacer. The photoresist layer is composed of an electrolyte containing resist. The charged gate is soaked in the electrolyte containing resist to form the photoresist spacer on the gate. However, this process is complicated, expensive and hard to control in manufacturing.
Also, U.S. Pat. No. 5,320,974 (Hori et al.) teaches a method of implanting impurities around a gate after an oxide spacer is removed. U.S. Pat. No. 5,286,664 (Horiuchi) shows a process of fabricating an asymmetrical LDD-MOSFET of the type in which a diffused low-doped layer is provided only on the drain side. In a MOSFET-formed region, after forming a gate electrode, using a photoresist film covering one sidewall of the gate electrode and the vicinity thereof, ion implantation is performed to form a diffused lightly-doped layer.
However, there is still a need for an improved LDD process that eliminates the problems associated with the convention al spacer and spacer etch processes.